1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a method of forming an insulating layer to control the step profile of a hole therethrough and a method of fabricating a thin film transistor using the same.
2. Discussion of the Related Art
As an information society develops, so increases the demand for information displays. Recently, many efforts have been made to research and develop various flat display panels, such as a liquid crystal display (LCD), a plasma display panel (PDP), a electroluminescent display (ELD), a vacuum fluorescent display (VFD), and the like. Due to the characteristics or advantages of a high quality color image, low weight, compact size, and low power consumption, an LCD is typically used instead of a cathode ray tube (CRT) for an image display of a moving picture. For example, an LCD can be utilized in devices that receive video or broadcast signals, such as televisions, computer monitors, and the like. An LCD can have high resolution, high brightness, a wide screen, as well as the characteristics of low weight, compactness, and low power consumption so as to be a general purpose display.
Such a general purpose LCD device includes a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel. First and second glass substrates are bonded to each other so as to leave a predetermined space therebetween and a liquid crystal layer is injected between the first and second glass substrates to form the liquid crystal panel. Formed on the first glass substrate or TFT array substrate are a plurality of gate lines arranged in one direction to leave a predetermined interval between each other. A plurality of data lines are arranged on the first glass substrate in a direction vertical to the gate lines to leave a predetermined interval between each other. A plurality of pixel electrodes formed like a matrix are positioned in pixel areas defined between the gate and data lines, respectively. A plurality of thin film transistors switched by signals from the gate lines to transfer signals of the data lines to the pixel electrodes are also positioned respectively in the pixels areas. Formed on the second glass substrate or color filter substrate are a black matrix layer for preventing light leakage from areas other than the pixel areas, an RIG/B color filter layer for realizing colors, and a common electrode for realizing an image together with the pixel electrodes. In the case of a horizontal electric field type liquid crystal display device, the common electrode is formed on the first glass substrate.
The above-constituted first and second substrates are separated from each other by spacers, and bonded to each other through a sealant. Liquid crystal is then injected between the first and second substrates. The thin film transistor of the liquid crystal display device is mainly used as a switching device. A semiconductor layer of the thin film transistor is formed of amorphous silicon, which enables the fabrication of small-scaled TFT-LCD. However, amorphous silicon has a low mobility, which adversely affects the operation of a wide-screen TFT-LCD. Therefore, many efforts have been made to research and develop a polysilicon thin film transistor (TFT) using a polysilicon layer having an excellent mobility as a semiconductor layer. Such a polysilicon TFT facilitates both the fabrication and operation of a wide-screen TFT-LCD, and enables the integration of a driving integrated circuit (IC) on a TFT array substrate to provide for high integrity and reduced costs of manufacturing.
In general, a polysilicon layer can be formed by two methods. The first method is depositing polysilicon directly on a substrate. The second method is to deposit amorphous silicon on a substrate and then crystallize the deposited amorphous silicon into polysilicon.
A polysilicon TFT includes a gate electrode separated from an active layer by an insulating layer. Source/drain electrodes contact the active layer through the insulating layer, which separates the active layer from the gate electrode. The insulating layer is mainly formed of an inorganic insulating layer, such as silicon nitride (SiNx) or silicon oxide (SiOx). The inorganic insulating layer has excellent handling characteristics, a high insulation withstanding voltage and high metal adhesion.
A method of forming an insulating layer and a method of forming polysilicon TFT using the same insulating layer according to related art are explained in reference to FIGS. 1 and 2A–2F. A cross-sectional view for explaining a method of forming an insulating layer hole 9 in an insulating layer 6 according to related art is shown in FIG. 1. An insulating layer 6, as shown in FIG. 1, is deposited uniformly on a glass substrate 1 at 300˜400° C. by plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or sputtering using silane (SiH4) gas. The insulating layer 6 formed on the glass substrate 1 is an inorganic insulating layer, such as silicon nitride (SiNx) or silicon oxide (SiOx). Then, a photoresist 2 is coated on the insulating layer and patterned via exposure and development to form a photoresist hole 7 in the photoresist 2 for defining a hole in the insulating layer 6. A portion of the insulating layer 6 is removed selectively by a wet etch using the patterned photoresist 2 as a mask to form a insulating layer hole 9 in the insulating layer 6 and thus expose a portion of the glass substrate 1 commensurate with the photoresist hole 7 in the photoresist 2.
As shown in FIG. 1, when the insulating layer 6 is removed by wet etch, more of the upper portion of the insulating layer 6 is removed than a lower portion of the insulating layer 6 such that the insulating layer hole 9 has a poor step profile, which is much wider at the top of the contact hole than at the bottom of the insulating layer hole 9 and is not very sharp. The step profile, as shown in FIG. 1, is not very sharp since the side 9a of the insulating layer hole travels a distance L along the substrate 1 from the top edge of the insulating layer hole 9 to a bottom edge of the insulating layer hole 9 that is much greater than the thickness T of the insulating layer 6. A step profile of the insulating layer hole is sharper as L/T gets closer to 0. The poor step profile, as shown in FIG. 1, can occur because the wet etch is active for a longer period on the upper portion of the insulating layer since etching proceeds through the upper portion of the insulating layer to the lower portion of the insulating layer.
The same poor step profile, as shown in FIG. 1, can also be a result of or further exacerbated by an insulating layer 6 formed of SiOx having poor adhesion to the photoresist 2 such that the etchant penetrates between the insulating layer 6 and photoresist 2. Thus, the etch rate of the upper portion of the insulating layer 6, particularly at the upper edge of the insulating layer hole 9 will be accelerated because of the proximity of both a side surface and a top surface being etched. Hence, the step profile of the insulating layer hole 9 will have rounded top edges and/or long step profile, as shown in FIG. 1.
FIGS. 2A to 2F illustrate cross-sectional views of forming a polysilicon thin film transistor according to related art. The amorphous silicon (—Si) is deposited on an entire surface of a glass substrate 11 to form an amorphous silicon layer. Annealing is carried out using an excimer laser to crystallize the amorphous silicon layer into a polysilicon layer. The polysilicon layer is then patterned selectively to form an active layer 13, as shown in FIG. 2A. Subsequently, a first insulating layer 14 is formed on an entire surface including the active layer 13 by depositing an inorganic insulating layer such as silicon nitride (SiNx) or silicon oxide (SiOx) at 300˜400° C. by PECVD, LPCVD, sputtering, or the like using silane (SiH4) gas.
Referring to FIG. 2B, an electrically conductive material such as Al, Al alloy, or the like is deposited on an entire surface including the first insulating layer 14, and then patterned selectively by photolithography to form a gate electrode 15 on a predetermined portion over the active layer 13. Subsequently, n-type or p-type impurity ions are implanted in the active layer 13 using the gate electrode 15 as a mask. The impurity ions implanted in portions of the active layer 13 corresponding to both sides of the gate electrode 15 become source/drain regions 13a and 13c, and the remaining portion of the active layer 13 blocked by the gate electrode 15 to have no impurity ions implanted therein becomes a channel region 13b. 
As shown in FIG. 2C, a second insulating layer 16 is formed by depositing an inorganic insulating layer such as silicon nitride, silicon oxide, or the like on an entire surface including the gate electrode 15. The second insulating layer 16 can be deposited by the same depositing method as for the first insulating layer 14. Then, a photoresist 12 is coated on an entire surface including the second insulating layer 16. Subsequently, the photoresist 12 is patterned by exposure and development to define a contact areas 17 with holes in the photoresist 12, as shown in FIG. 2D.
Referring to FIG. 2E, the second and first insulating layers 16 and 14 are selectively removed to form contact holes 19 that expose predetermined surfaces of the source/drain regions 13a and 13c, respectively, using the patterned photoresist 12 as a mask. In this instance, the etching process for forming the contact holes 19 is a process of removing a portion of the insulating layer 16, defined as a contact area 17 by the photoresist 12, using a chemical solution. An etching process using a chemical solution is called a wet etch as opposed to a process using plasma, which is called a dry etch. The wet etch is classified into a dipping and spraying. The dipping method is carried out in such a manner that a substrate is dipped into a solution bath filled with a chemical solution. The spray method is carried out in such a manner that a chemical solution is sprayed on a substrate.
Subsequently, a metal layer is deposited on a glass substrate 11 including the contact holes 19, regardless of which etching method is used. Photo and etching processes are then carried out to form source and drain electrodes 18a and 18c connected to the source and drain regions 13a and 13c, respectively. The source and drain electrodes 18a and 18c are isolated electrically from the gate electrode 15 by the second insulating layer 16. Thus, the polysilicon thin film transistor using polysilicon as a semiconductor layer in the related art is completed by the above-explained process, as shown in FIG. 2F.
A liquid crystal display device can include the polysilicon thin film transistor described above on the first substrate as the switching device of a pixel. As also described in the foregoing explanation, the first and second insulating layers 14 and 16 are selectively etched by wet etch. The wet etch is an isotropic etching process using a chemical solution so that equipment costs are reduced and the productivity is increased. However, the rectangular dimensions or step profile of an etched contact hole is degraded. For example, referring again to FIG. 2E, a chemical reaction occurs rapidly when the chemical solution flows in, whereby the second insulating layer 16 beneath the photoresist 12 is etched to a diameter significantly beyond the designed specification or contact area 17 defined by the photoresist while the first insulating layer 14 is under-etched. Hence, the rectangular dimensions or step profile of the contact hole through the first and second insulating layers are degraded.
Thus, a poor step profile or large diameters for each of the contact holes to a polysilicon thin film transistor increases the size of the TFT, as well as decreases the space for a pixel electrode. A decrease in the size of a pixel or increase in the size of a TFT reduces the resolution of the LCD panel. Therefore, it is important to increase the sharpness of a step profile for each of the contact holes to TFT.
In order to overcome the problem of contact holes with poor step profiles, dry etch using plasma has been introduced. The dry etch, which is anisotropic, has the advantage of step profile control and the disadvantage of etching the photoresist such that the pattern is affected. Another method include the steps of carrying out wet etch and then etching an under-etched portion with a dry etch to equalize the etch selectivity ratio between the first and second insulating layers. However, such a method needs an additional step, which increases process costs as well as requires two completely different types of processing equipment.